1. Field of the Invention
This invention relates to power amplifiers and more particularly to high-power, monolithic, integrated circuit (IC) power amplifiers.
2. Background Art
Certain telecommunications standards have been developed in the United States to provide high-speed digital access between customers and a central office. One example is the Asymmetric Digital Subscriber Loop (ADSL) standard, which provides a data rate of approximately 6 Mb in the direction from the central office to the customer. As a result of the high data rate, ADSL has become one of the preferred standards for supplying Internet service over a standard copper wire twisted pair.
Although it offers a high data rate, the ADSL standard requires that the line-driving amplifier at the central office be able to supply a signal of approximately 20 dBm (power with respect to a reference level of 1 mW) in power with a peak-to-rms average voltage ratio (PAR) of 5.33:1. In order to accommodate the required power output level and PAR, two line-driving amplifiers, or a line-driver pair, are commonly used in a bridge configuration with a 1:2 step-up transformer between the amplifiers and the line.
One disadvantage of this conventional arrangement is its need for power as the number of customers grows. In the near future, for example, it is expected that several thousand customers may require ADSL service from the same central office. The possibility of expending several kilowatts of power just to operate the ADSL line-drivers has therefore become a major concern regarding this type of digital service. Much research effort has therefore been applied to the problem of increasing the efficiency of monolithic, integrated circuit (IC) power amplifiers for ADSL applications.
In one known circuit arrangement, the output stage of an operational amplifier is connected to an approximately constant supply voltage that is greater in magnitude than the maximum zero-to-peak output voltage. The amount by which the supply voltage exceeds the maximum output voltage is commonly known as the voltage headroom required for the stage. For example, a typical value for the voltage headroom in prior art circuits is 3V. The zero-to-peak voltage for an ADSL amplifier in the central office is approximately 8.42V. The minimum power supply voltage for such an arrangement would therefore be approximately 11.42V. The supply voltage, given some initial voltage setting inaccuracy, may therefore be nominally 12V.
Because the average current required from each power supply (+/xe2x88x9212V) in the amplifier pair is approximately 28.5 mA for the ADSL central office, the minimum power possible for a 12V supply would be 4xc3x9712Vxc3x9728.5 mA =1.36 W. This would be the minimum power given ideal xe2x80x9cClass Cxe2x80x9d operation of the output stage and without providing additional power for any amplifier current bias circuits. Because ADSL power amplifiers require low output distortionxe2x80x94typically better than 70 dB for signal to noise-and-distortion ratiosxe2x80x94xe2x80x9cClass Cxe2x80x9d operation is not practical. It is therefore understandable why, despite considerable efforts, many manufacturers have not been possible to reduce power consumption for ADSL central office line driving amplifier pairs significantly below 1.5 W.
One known method for reducing power consumption is the elimination, or substantial reduction, in the value of the load-matching termination resistor that is usually included in the circuit. Several circuits have been described in the technical literature that use using active electronic circuits to emulate the effect of the termination resistor, and thereby allow its value to be reduced by as much as a factor of 10. These circuit combinations may be driven by a conventional driver with 8.5V peak output voltage, but transformer ratios closer to 1:1 allow a significant reduction in peak currents for output drivers in the central office. Such circuits are capable of achieving power levels in the range close to 1 watt.
Another possibility for reducing driver output power is commonly described as xe2x80x9cClass Gxe2x80x9d operation. In Class G, the output stage is switched from a lower to a higher voltage supply when output voltage demand is high. If the output driver can be supplied with current from the lower supply for a major fraction of the output waveform, a significant power savings can result. On the other hand, if the switching is done abruptly, significant voltage transients may arise on the supply terminals of the output driver device. This in turn results in increasing noise and distortion components well beyond acceptable limits.
The object of a co-pending application by the present inventor is to reduce switching transients in the output driver supply voltage by providing a linear power switching circuit that operates to maintain a nearly constant headroom, that is, difference between the voltage supply terminal and signal power output terminal, in the output power driver. Unfortunately, the capability of supplying nearly a constant headroom over the entire dynamic output range implies providing as much headroom at the lower switch-over voltage as at the higher maximum output driver voltage.
A very large area bipolar driver transistor pair might only require approximately 800 mV of headroom at maximum output current, but the pair might be so large that is precludes integration with more than one, and possibly up to four other driver transistor pairs on a single bipolar integrated circuit. By providing more headroom, 1.5V for example, at maximum output, it would be possible to tolerate a larger collector resistance and allow construction of each driver using significantly less chip area.
Unfortunately, a circuit that provided a constant headroom for the output driver of 1.5V and also consumed an additional 0.5V of headroom for the power switch could provide a maximum switch-over voltage of only about 3V. Because of the shape of the normal probability distribution for the ADSL signal statistics, a driver with a switch-over voltage of 3V and a maximum voltage of 9V, for example, would require that four times more of the output duty cycle must be supplied from the inefficient, high voltage supply than would a driver with a switch-over voltage of 4V.
What is needed is therefore an arrangement that provides less headroom at switch-over and more headroom at maximum output, with predictable dynamic headroom voltage control over the whole signal output range. Minimizing headroom at crossover and providing considerably more, but carefully controlled, headroom that increases to maximum output would make possible a significant reduction in the power consumed by the amplifier and also minimize the layout area required by the high-current output devices. The combination of low power dissipation and low integrated circuit areas is essential to achieving higher than present levels of integration in bipolar output drivers for telecommunications applications. This invention provides such an arrangement.
In the amplifier according to the invention, collector voltage at the output stage is dynamically controlled to be greater than the emitter voltage by a difference voltage that increases proportionally as output voltage increases above the switch-over threshold. This difference voltage is commonly referred to as xe2x80x9cheadroom.xe2x80x9d The dynamic headroom control circuitry preferably includes circuitry for predictably setting and controlling the headroom voltage at switch-over and smoothly increasing the headroom voltage up to maximum output voltage. Providing low headroom at switch-over is a key to achieving high power efficiency and low power dissipation. Providing increased headroom at maximum voltage output is a key to reducing the integrated circuit area required by the high current output drivers.
A monolithic integrated circuit amplifier according to the invention has an input signal and an output signal, as well as a gain stage. The gain stage has a gain stage output signal and, as an input, the amplifier input signal. A buffer stage produces an amplifier output signal and has, as its input signal, the gain stage output signal. A driver output stage, included within the output buffer stage, has at least a first power output transistor.
First and second voltage supplies are included, the second voltage supply having a relatively higher magnitude than the first. A first power control circuit is connected to both the first and second voltage supplies, and to the driver output stage through a regulator bus. The first power control circuit includes first and second switching circuits connected to the first and second voltage supplies, respectively. Outputs of the first and second switching circuits are both connected to the regulator bus; these outputs are preferably and respectively one terminal of a diode and the emitter of a bipolar (or MOS equivalent) transistor. The diode may be of conventional PN junction silicon-diode construction or may preferably be a Schottky diode.
When an output demand voltage is less than a predetermined switch-over threshold, current to the driver output stage is provided substantially entirely from the first voltage supply via the first switching circuit and the regulator bus. When the output demand voltage is greater than the switch-over threshold, current to the output driver stage is provided substantially entirely from the second voltage supply, via the second switching circuit and the regulator bus.
When in a first mode of operation, the first switching circuit is conducting and supplying the current to the output driver stage, the voltage on the regulator bus itself blocks current output from the second switching circuit.
When in a second mode of operation, the second switching circuit is conducting and supplying the current to the output driver stage, the voltage on the regulator bus itself blocks current output from the first switching circuit.
In the preferred embodiment of the invention, the first and second voltage supplies comprise a first dual voltage supply. The regulator bus connecting the first dual voltage supply to the power amplifier output via a first power control circuit is thereby a first regulator bus. The amplifier then preferably further includes a second dual voltage supply, including third and fourth voltage supplies having the same amplitudes but opposite polarity relative to the first and second voltage supplies, respectively; and a second power control circuit having the substantially identical components and connections but opposite polarities relative to the first power control circuit. The invention then further includes, in the buffer stage, a common output voltage terminal for both power control circuits.
For each power control circuit, there is then preferably provided: a driver output transistor that has an emitter, a collector, and a base (or MOS equivalents); an optional output resistor connected between the emitter of the output transistor and the voltage output terminal; and an emitter-follower transistor connected to the respective second voltage supply and forming an emitter-follower driver circuit for the output transistor.
According to one aspect of the invention, in a second mode of operation, the voltage at the collector (or MOS equivalent) of the driver output transistor is dynamically controlled to be greater than the voltage at the emitter (or MOS equivalent) of the driver output transistor by an amount that increases as the driver output stage voltage delivered to the load increases. This provides increased headroom voltage for the driver output transistor in order to maintain the transistor just above saturation as the demand for output current increases.
According to yet another aspect of the invention, in a first mode of operation, the voltage at the collector (or MOS equivalent) of the driver output transistor may be dynamically controlled to be greater than the voltage at the emitter (or MOS equivalent) of the transistor by a minimum amount that is approximately equal to one diode drop. This prevents substantial forward biasing of the base-collector diode and large parasitic capacitances that would otherwise result from such a forward biased condition.
According to yet another aspect of the invention, the transition from the first to second mode of operation occurs at a relatively high driver output voltage or low driver output driver transistor collector-to-emitter voltage. This is because, at the lower-than-maximum output currents occurring at this transition, large collector-to-emitter voltage is not required. The collector-to-emitter voltage is adjustable to be maintained just greater than a diode drop at the transition and is capable of rising to a few volts at full output.
The last mentioned aspect of the invention is particularly advantageous, because output power efficiency increases in proportion to the fraction of the duty cycle over which the circuit is in the first mode of operation. When the transition can occur at a relatively higher output voltage, that duty cycle fraction is relatively higher than would be the case with a lower transition voltage.
In the preferred embodiment of the invention, with the first voltage supply set, for example, to +/xe2x88x925V and the second voltage supply set to +/xe2x88x9212V the switch-over voltage may be approximately 4V, giving a maximum voltage of approximately 9V.
Because the maximum voltage in an ADSL signal is 5.33 times its standard deviation, a switch-over voltage of only 3V would correspond to approximately 1.77 times the signal standard deviation. A randomly distributed ADSL signal exceeds 1.77 times it standard deviation for approximately 8 percent of its duty cycle.
By comparison, a switch-over voltage of approximately 4V corresponds to approximately 2.3 times the signal standard deviation. The normal probability statistics of a randomly distributed ADSL signal are such as to cause the fraction of the total duty cycle to drop sharply as the switch-over voltage is increased, to approximately 2 percent, for the fraction of the duty cycle that the switch-over voltage was exceeded.
The significant power savings made possible by realizing a duty cycle substantially less than 8 percent, when combined with active load termination methods, enable driver power levels for ADSL below 500 mW. Moreover, a combined package power dissipation limit of approximately 2 watts makes it possible to combine as many as four line drivers in a single package. The present invention therefore represents enabling technology that will allow the construction of quad ADSL integrated-circuit line drivers.